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1-mbit (64k x 16) static ram cy62126dv30 mobl ? cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05230 rev. *g revised may 30, 2005 features ? temperature ranges ? industrial: ?40c to 85c ? automotive: ?40c to 125c ? very high speed: 45 ns ? wide voltage range: 2.2v to 3.6v ? pin compatible with cy62126bv ? ultra-low active power ? typical active current: 0.85 ma @ f = 1 mhz ? typical active current: 5 ma @ f = f max ? ultra-low standby power ? easy memory expansion with ce and oe features ? automatic power-down when deselected ? packages offered in a 48-ball fbga, 56-lead qfn and a 44-lead tsop type ii ? also available in lead-free packages functional description [1] the cy62126dv30 is a high-performance cmos static ram organized as 64k words by 16 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-dow n feature that significantly reduces power consumption by 90% when addresses are not toggling. the device can be put into standby mode reducing power consumption by more than 99% when deselected (ce high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce high), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high) or during a write operation (ce low and we low). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. note: 1. for best-practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypr ess.com. logic block diagram 64k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 2048 x 512 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce we ble bhe a 0 a 1 a 9 a 10
cy62126dv30 mobl ? document #: 38-05230 rev. *g page 2 of 13 product portfolio pin configurations [3, 4] notes: 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25c. 3. nc pins are not connected to the die. 4. e3 (dnu) can be left as nc or v ss to ensure proper operation. (expansion pins on fbga pa ckage: e4 - 2m, d3 - 4m, h1 - 8m, g2 - 16m, h6 - 32m). product range v cc range (v) speed (ns) power dissipation operating, i cc (ma) standby, i sb2 ( a) f = 1 mhz f = f max min. typ. max. typ. [2] max. typ. [2] max. typ. [2] max. cy62126dv30l industrial 2.2 3.0 3.6 45 0.85 1.5 6.5 13 1.5 5 cy62126dv30ll industrial 45 0.85 1.5 6.5 13 1.5 4 cy62126dv30l industrial 2.2 3.0 3.6 55 0.85 1.5 5 10 1.5 5 cy62126dv30l automotive 55 0.85 1.5 5 10 1.5 15 cy62126dv30ll industrial 55 0.85 1.5 5 10 1.5 4 cy62126dv30l industrial 2.2 3.0 3.6 70 0.85 1.5 5 10 1.5 5 cy62126dv30ll industrial 70 0.85 1.5 5 10 1.5 4 we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe nc a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h fbga (top view) nc dnu v cc nc we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view tsop ii (forward) 12 13 41 44 43 42 16 15 29 30 v cc a 15 a 14 a 13 a 12 nc a 4 a 3 oe v ss a 5 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe nc a 1 a 0 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 nc v ss i/o 6 i/o 4 i/o 5 i/o 7 a 6 a 7 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 8 a 9 a 10 a 11
cy62126dv30 mobl ? document #: 38-05230 rev. *g page 3 of 13 pin configurations (continued) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ble i/o 15 i/o 14 i/o 13 i/o 12 v ss v cc i/o 11 i/o 10 i/o 9 i/o 8 a 7 a 6 nc ce i/o 0 i/o 1 i/o 2 i/o 3 v cc v ss i/o 4 i/o 5 i/o 6 i/o 7 we a 0 a 1 bhe oe a 8 a 9 nc a 10 a 11 nc a 12 a 13 a 14 a 15 nc nc nc nc nc a 5 nc nc a 4 dnu nc nc a 3 nc nc a 2 56-pin qfn
cy62126dv30 mobl ? document #: 38-05230 rev. *g page 4 of 13 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential .............................................................. ? 0.3 to 3.9v dc voltage applied to outputs in high-z state [6] .................................... ? 0.3v to v cc + 0.3v dc input voltage [6] ................................ ? 0.3v to v cc + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range range ambient temperature (t a ) v cc [7] industrial ? 40c to +85c 2.2v to 3.6v automotive ? 40c to +125c 2.2v to 3.6v dc electrical characteristics (over the operating range) parameter description test conditions cy62126dv30-45 cy62126dv30-55 cy62126dv30-70 unit min. typ. [5] max. min. typ. [5] max. min typ. [5] max. v oh output high voltage 2.2 < v cc < 2.7 i oh = ? 0.1 ma 2.0 2.0 2.0 v 2.7 < v cc < 3.6 i oh = ? 1.0 ma 2.4 2.4 2.4 v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma 0.4 0.4 0.4 v 2.7 < v cc < 3.6 i ol = 2.1 ma 0.4 0.4 0.4 v ih input high voltage 2.2 < v cc < 2.7 1.8 v cc + 0.3 1.8 v cc + 0.3 1.8 v cc + 0.3 v 2.7 < v cc < 3.6 2.2 v cc + 0.3 2.2 v cc + 0.3 2.2 v cc + 0.3 v il input low voltage 2.2 < v cc < 2.7 ? 0.3 0.6 ? 0.3 0.6 ? 0.3 0.6 v 2.7 < v cc < 3.6 ? 0.3 0.8 ? 0.3 0.8 ? 0.3 0.8 i ix input leakage current gnd < v i < v cc ind?l ? 1 +1 ? 1 +1 ? 1 +1 a auto ? 4 +4 a i oz output leakage current gnd < v o < v cc , output disabled ind?l ? 1 +1 ? 1 +1 ? 1 +1 a auto ? 4 +4 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.6v, i out = 0 ma, cmos level 6.5 13 5 10 5 10 ma f = 1 mhz 0.85 1.5 0.85 1.5 0.85 1.5 i sb1 automatic ce power-down current? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v, v in < 0.2v, f = f max (address and data only), f = 0 (oe , we , bhe and ble ) l ind?l 1.5 5 1.5 5 1.5 5 a auto 1.5 15 ll 1.5 4 1.5 4 1.5 4 i sb2 automatic ce power-down current? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.6v l ind?l 1.5 5 1.5 5 1.5 5 a auto 1.5 15 ll 1.5 4 1.5 4 1.5 4 notes: 5. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25c. 6. v il(min.) = ? 2.0v for pulse durations less than 20 ns., v ih(max.) = v cc + 0.75v for pulse durations less than 20 ns. 7. full device operation requires linear ramp of v cc from 0v to v cc(min) & v cc must be stable at v cc(min) for 500 s.
cy62126dv30 mobl ? document #: 38-05230 rev. *g page 5 of 13 ac test loads and waveforms [9] data retention waveform notes: 8. tested initially and after any design or proc es changes that may affect these parameters. 9. test condition for the 45-ns part is a load capacitance of 30 pf. 10. full device operation requires linear v cc ramp from v dr to v cc(min.) >100 s. capacitance [8] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz v cc = v cc(typ) 8 pf c out output capacitance 8 pf thermal resistance parameter description test conditions qfn tsop fbga unit ja thermal resistance (junction to ambient) [8] still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 22.08 55 76 c/w jc thermal resistance (junction to case) [8] 5.03 12 11 c/w data retention characteristics parameter description conditions min. typ .[2] max. unit v dr v cc for data retention 1.5 v i ccdr data retention current v cc =1.5v, ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v l ind?l 4 a l auto 10 ll ind?l 3 t cdr [8] chip deselect to data retention time 0 ns t r [10] operation recovery time 100 s v cc typ v cc output r2 50 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: th venin equivalent all input pulses r th r1 rise time: 1 v/ns fall time: 1 v/ns parameters 2.5v 3.0v unit r1 16600 1103 ohms r2 15400 1554 ohms r th 8000 645 ohms v th 1.2 1.75 volts v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r ce v cc
cy62126dv30 mobl ? document #: 38-05230 rev. *g page 6 of 13 switching characteristics (over the operating range) [11] parameter description cy62126dv30-45 [9] cy62126dv30-55 cy62126dv30-70 unit min. max. min. max. min. max. read cycle t rc read cycle time 45 55 70 ns t aa address to data valid 45 55 70 ns t oha data hold from address change 10 10 10 ns t ace ce low to data valid 45 55 70 ns t doe oe low to data valid 25 25 35 ns t lzoe oe low to low z [12] 5 5 5 ns t hzoe oe high to high z [12, 13] 15 20 25 ns t lzce ce low to low z [12] 10 10 10 ns t hzce ce high to high z [12, 13] 20 20 25 ns t pu ce low to power-up 0 0 0 ns t pd ce high to power-down 45 55 70 ns t dbe ble /bhe low to data valid 25 25 35 ns t lzbe ble /bhe low to low z [12] 5 5 5 ns t hzbe ble /bhe high to high-z [12, 13] 15 20 25 ns write cycle [14] t wc write cycle time 45 55 70 ns t sce ce low to write end 40 40 60 ns t aw address set-up to write end 40 40 60 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 35 40 50 ns t bw ble /bhe low to write end 40 40 60 ns t sd data set-up to write end 25 25 30 ns t hd data hold from write end 0 0 0 ns t hzwe we low to high z [12, 13] 15 20 25 ns t lzwe we high to low z [12] 10 10 5 ns notes: 11. test conditions assume signal transition time of 1v/ns or less, timing reference levels of v cc(typ.) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol . 12. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe . 13. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 14. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edg e of the signal that terminates the write.
cy62126dv30 mobl ? document #: 38-05230 rev. *g page 7 of 13 switching waveforms read cycle no. 1 (address transition controlled) [15, 16] read cycle no. 2 (oe controlled) [16, 17] notes: 15. device is continuously selected. oe , ce = v il , bhe , ble = v il . 16. we is high for read cycle. 17. address valid prior to or coincident with ce , bhe , ble transition low. address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t lzbe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current t hzbe bhe /ble t lzoe address t doe t lzoe t dbe
cy62126dv30 mobl ? document #: 38-05230 rev. *g page 8 of 13 write cycle no. 1 (we controlled [13, 14, 17, 18, 19] write cycle no. 2 (ce controlled) [13, 14, 17, 18, 19] notes: 18. data i/o is high-impedance if oe = v ih . 19. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 20. during the don't care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in valid note 20 bhe /ble t bw t sce t hd t sd t pwe t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 20 bhe /ble t bw t sa
cy62126dv30 mobl ? document #: 38-05230 rev. *g page 9 of 13 write cycle no. 3 (we controlled, oe low) [18, 19] write cycle no. 4 (bhe -/ble -controlled, oe low) [17, 18] switching waveforms (continued) data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 20 t bw bhe /ble data i/o address t hd t sd t sa t ha t aw t wc ce we data in valid note 20 t bw bhe /ble t sce t pwe
cy62126dv30 mobl ? document #: 38-05230 rev. *g page 10 of 13 truth table ce we oe bhe ble inputs/outputs mode power h x x x x high z deselect/power-down standby (i sb ) l x x h h high z output disabled active (i cc ) l h l l l data out (i/o o ?i/o 15 ) read active (i cc ) l h l h l data out (i/o o ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (i/o o ?i/o 15 ) write active (i cc ) l l x h l data in (i/o o ?i/o 7 ); i/o 8 ?i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write active (i cc ) ordering information speed (ns) ordering code package name package type operating range 45 cy62126dv30ll-45bvi bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) industrial cy62126dv30ll-45bvxi bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) (pb-free) cy62126dv30ll-45zxi z44 44-lead tsop type ii (pb-free) cy62126dv30ll-45lfxi lf56 56-pin qfn (pb-free) 55 cy62126dv30l-55bvi bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) industrial cy62126dv30ll-55bvi bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) cy62126dv30ll-55bvxi bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) (pb-free) cy62126dv30l-55zi z44 44-lead tsop type ii cy62126dv30ll-55zi z44 44-lead tsop type ii cy62126dv30ll-55zxi z44 44-lead tsop type ii (pb-free) cy62126dv30l-55zse z44 44-lead tsop type ii automotive cy62126dv30l-55zsxe z44 44-lead tsop type ii (pb-free) cy62126dv30l-55bvxe bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) (pb-free) cy62126dv30ll-55lfxi lf56 56-pin qfn (pb-free) industrial 70 cy62126dv30l-70bvi bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) industrial cy62126dv30ll-70bvi bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) cy62126dv30ll-70bvxi bv48a 48-ball fine pitch bga (6 mm x 8 mm x 1 mm) (pb-free) CY62126DV30L-70ZI z44 44-lead tsop type ii cy62126dv30ll-70zi z44 44-lead tsop type ii cy62126dv30ll-70zxi z44 44-lead tsop type ii (pb-free) cy62126dv30ll-70lfxi lf56 56-pin qfn (pb-free)
cy62126dv30 mobl ? document #: 38-05230 rev. *g page 11 of 13 package diagrams 48-lead vfbga (6 x 8 x 1 mm) bv48a 51-85150-*b 44-pin tsop ii z44 51-85087-*a
cy62126dv30 mobl ? document #: 38-05230 rev. *g page 12 of 13 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagrams (continued) mobl is a registered trademark, and mobl2 and more battery life are trademarks of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. 0.80[0.031] 7.70[0.303] 7.90[0.311] a c 1.00[0.039] max. n seating plane n 2 0.18[0.007] 0.50[0.020] 1 1 0.08[0.003] 0.50[0.020] 0.05[0.002] max. 2 (4x) c 0.24[0.009] 0.20[0.008] ref. 0.80[0.031] max. pin1 id 0-12 6.45[0.254] 8.10[0.319] 7.80[0.307] 6.55[0.258] 0.45[0.018] 0.20[0.008] r. 8.10[0.319] 7.90[0.311] 7.80[0.307] 7.70[0.303] dia. 0.28[0.011] 0.30[0.012] 6.55[0.258] 6.45[0.254] 0.60[0.024] top view bottom view side view e-pad (pad size vary by device type) 51-85144-*d 56-lead qfn 8 x 8 mm lf56a
cy62126dv30 mobl ? document #: 38-05230 rev. *g page 13 of 13 document history page document title: cy62126dv30 mobl ? 1- mbit (64k x 16) static ram document number: 38-05230 rev. ecn no. issue date orig. of change description of change ** 117689 08/27/02 jui new data sheet *a 127313 06/13/03 mpr changed from ad vanced status to preliminary. changed i sb2 to 5 a (l), 4 a (ll) changed i ccdr to 4 a (l), 3 a (ll) changed c in from 6 pf to 8 pf *b 128340 07/22/03 jui changed from preliminary to final add 70-ns speed, updated ordering information *c 129002 08/29/03 cdy changed i cc 1 mhz typ from 0.5 ma to 0.85 ma *d 238050 see ecn aju fixed typo: changed t dbe from 70 ns to 35 ns *e 316039 see ecn pci added 45-ns speed bin in ac, dc and ordering information tables added footnote #8 on page #4 added pb-free package ordering information on page # 9 changed 44-pin tsop-ii package name from z44 to zs44 *f 335861 see ecn syt added temperature ranges in the features section on page # 1 added automotive product information for cy62126dv30-l for 55 ns added i sb1 and i sb2 values for automotive range of cy62126dv30-l for 55 ns added automotive information for i ccdr in the data retention characteristics table added pb-free packages in the ordering information changed 44-pin tsop-ii package name from zs44 to z44 *g 357256 see ecn pci added pin configuratio n and package diagram for 56-lead qfn package updated thermal characteristics and ordering information table added automotive specs for i ix and i oz in the dc electrical characteristics table on page# 4

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